The present invention relates generally to nonvolatile memory cell structure, array structure, and operation. More particularly, the present invention relates to improved 1T1b and 2T2b flash-based Electrical Erasable Programmable Read Only Memory (EEPROM) data-oriented cell structures, array structures, and operations.
Nonvolatile memory is well known in the art. The different types of nonvolatile memory that employ a charge retention mechanism include Read-Only-Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), NOR Flash Memory, and NAND Flash Memory. The charge retention mechanism may be charge storage, as in a floating gate memory cell, a so-called Flash-based cell.
The NAND Flash memory cell design has several advantages. Firstly, its cell size is highly scalable and is able to have a cell size that is a factor of approximately four times (4×) larger than the minimum feature size (λ2) of the manufacturing technology. This has held in technologies with feature sizes from 0.25 μm down to 20 nm. This is the smallest nonvolatile memory cell when compared to other nonvolatile cell types. Secondly, NAND Flash memory cell design uses a low-current Fowler-Nordheim tunneling phenomena for both program and erase operations. The Fowler-Nordheim Tunneling allows the program and erase operations to be performed in relatively larger memory unit sizes and a faster speed. The Fowler-Nordheim erase operation is typically performed in a unit of a large sector with sizes ranging from 512 Kb to 2 Mb and 1 ms fast erase time in current specifications. The Fowler-Nordheim program is performed in a unit of a large page size varying from 512 B to 2 KB with a fast speed of 200 us typically in the current specifications.
By contrast, NOR Flash memory device is formed of an array of less-compact charge retaining transistors that are fundamentally connected in parallel, rather than serially in a NAND Flash memory array. Like a NAND Flash memory charge storage transistor, the NOR Flash memory charge storage transistor is also made of the stack-gate cell structure for the floating gate transistors. Each NOR Flash memory cell has a contact metallurgy at each drain and source node to connect each NOR Flash memory cell to the common bit lines and source lines. The cell size for the NOR Flash memory, therefore, is larger than the NAND Flash memory.
As is known in the art, an EEPROM memory array is structured to be a byte-wise erasable structure as compared to block-wise erasable NAND flash memory arrays. EEPROM memory array requires more die area than a NAND flash memory of the same capacity because each EEPROM memory cell pitch is much larger. Conversely, in a NAND flash memory array, the erase circuits are shared by large blocks of cells (often 512×8 bits).
Typically, the three types of nonvolatile memory structures are targeted three different storage markets and technologies are not compatible. The NAND Flash memory has been extensively used as a slow-serial-read, extreme high-density, block-alterable memory array for huge data storage. Conversely, the NOR Flash memory is used as a fast-random-read medium-high-density, sector-alterable memory array for program code storage. Unlike the NAND and NOR Flash memories, the EEPROM memory is broadly used as a fast-random-read, byte-alterable memory array for small data storage.
An EEPROM memory array design has certain disadvantages. The first disadvantage is a large cell size that is the largest among the nonvolatile memory structures. Currently, the EEPROM manufacturing technology process, in real production, is about four generations behind NOR Flash memory manufacturing technology and seven generations behind the NAND Flash memory manufacturing technology. The cell size will be relatively larger as technology migrates below 0.15 μm. In the manufacturing process node above and including 0.18 μm, the EEPROM cell has been realized with a cell area size of about 90 times the minimum feature size (λ2) but will have an area larger than 100 times the minimum feature size (λ2) when migrating below 0.15 μm.
The second disadvantage of the EEPROM memory array design is that a very high bit line programming voltage is required. The programming voltage is as high as 16 V in the cell channel region between its drain and source nodes for performing proper Fowler-Nordheim Program operation. As a result, the EEPROM memory array program operation is the most critical one as compared to NAND Flash memory array and NOR Flash memory array. The very high programming voltage requirement in cell's channel region between the drain and source prevents the EEPROM memory cell area from further scaling below the 0.13 μm minimum feature size. During a higher density page program operation, higher number of bit lines and one word line is charged to the very high programming voltage of 16V in the worst-case. The page size varies from 8 bytes in low-density 2 kb part to 256 Bytes for high-density parts such as 1-2 Mb with page program speed of around 1 ms.
One major advantage of the EEPROM memory design lies in the number of Program and Erase (P/E) endurance cycles. Currently a two-transistor FLOTOX-based EEPROM memory array can endure at least 1 million program-and-erase (P/E) cycles in units of byte or page. Therefore, the two-transistor EEPROM memory array is the best nonvolatile storage memory for those extremely high frequency changing rates of byte-alterable or page-alterable data applications. For example, a two floating gate tunnel oxide (FLOTOX) based EEPROM memory design has been developed for the market need of byte-alterable data-oriented application, keeping the advantage of 1M P/E endurance of traditional EEPROM memory as well as features of fast write speed and relative simple manufacture process. A recent trend for the byte-alterable EEPROM application demands a low-cost high-density storage solution that allows the scaling below 90 nm at higher temperature automotive environment. The drawback of the 2T FLOTOX-based EEPROM cell is its large cell size (for storing one bit) of 90λ2 and high bit line voltage level of about 16 V which limits its channel length scaling. Alternatively, an one floating gate transistor Flash-based EEPROM cell is proposed to reduce the cell size (for storing one bit) to about one-third of that, down to 30λ2. But current operation scheme of the corresponding 1T1b EEPROM cell array in the prior art still requires bit line inhibit voltage level as high as 16 V. Thus the stress to the source line select transistors and bit line select transistors is very high, imposing a big disadvantage of inferior of P/E endurance cycle of just about 300K. Therefore, improved operation schemes as well as new memory array architectures are needed and become objectives of the present invention.